KEYNOTE SPEAKER

Overhauling Multicores' Performance: Modeling and Load Balancing

Prof. Leonel Sousa
INESC-ID, Instituto Superior Tecnico, Universidade de Lisboa, Portugal

Abstract

Exploiting and leveraging the high performance capabilities of current and future computational systems with heterogeneous architectures and multi-level memory hierarchies is a real challenge. In this talk, some of these challenges are throughly addressed, and novel performance modeling and load balancing strategies are presented in order to allow efficient concurrent and cross-device collaborative computing. The efficiency of the parallel execution is analyzed not only for a single computing node with multi-core CPUs and several accelerators (such as GPUs), but also for multi-cluster environments with multiple of these heterogeneous nodes. The presented adaptive scheduling and load balancing techniques build several highly accurate partial performance models while converging towards the multi-level load distributions. These models are built at runtime and encapsulate the fundamental aspects of the parallel architectures when executing applications with diverse characteristics. Furthermore, for multicores with complex memory hierarchies, a novel insightful cache-aware performance modeling is presented, which graphically represents the practical limits of parallel processing on specific architecture. Finally, the usefulness of the presented approaches is experimentally assessed when the target is optimizing and characterizing the execution of a wide range of real-world applications from standard benchmark suites (SPEC CPU 2006, PARSEC and SPLASH), and several scientific kernels from the Intel MKL.

Biography of the Keynote Speaker

Leonel Sousa received the Ph.D. degree in Electrical and Computer Engineering from the Instituto Superior Tecnico (IST), Universidade de Lisboa (UL), Lisbon, Portugal, in 1996, where he is currently a Full Professor. He is also a Senior Researcher with the R\&D Instituto de Engenharia de Sistemas e Computadores (INESC-ID). His research interests include VLSI architectures, computer architectures, parallel computing, computer arithmetic, and signal processing systems. He has contributed to more than 200 papers in journals and international conferences, for which he got several awards - such as, DASIP’13 Best Paper Award, SAMOS’11 'Stamatis Vassiliadis' Best Paper Award, DASIP’10 Best Poster Award, and the Honorable Mention Award UTL/Santander Totta for the quality of the publications in 2009. He has contributed to the organization of several international conferences, namely as program chair, and general and topic chair, and has given keynotes in some of them. He has edited two special issues of international journals, and he is currently Associate Editor of the IEEE Transactions on Circuits and Systems for Video Technology, and of Springer journals JES and JRTIP. He is Fellow of the IET, a Senior Member of both IEEE and ACM, and Member of IFIP WG10.3 on concurrent systems.